HD6432138SW datasheet(35/1061 Pages) RENESAS

35 / 1061 page

Rev. 4.00 Jun 06, 2006 page xxxv of liv

Figures

Section 1 Overview

Figure 1.1

Internal Block Diagram of H8S/2138 Group.....................................................

Figure 1.2

Internal Block Diagram of H8S/2134 Group.....................................................

Figure 1.3

Pin Arrangement of H8S/2138 Group (FP-80A, TFP-80C: Top View) ............

Figure 1.4

Pin Arrangement of H8S/2134 Group (FP-80A, TFP-80C: Top View) ............

Section 2 CPU

Figure 2.1

CPU Operating Modes.......................................................................................

Figure 2.2

Exception Vector Table (Normal Mode) ...........................................................

Figure 2.3

Stack Structure in Normal Mode .......................................................................

Figure 2.4

Exception Vector Table (Advanced Mode) .......................................................

Figure 2.5

Stack Structure in Advanced Mode ...................................................................

Figure 2.6

Memory Map .....................................................................................................

Figure 2.7

CPU Registers ...................................................................................................

Figure 2.8

Usage of General Registers ...............................................................................

Figure 2.9

Stack ..................................................................................................................

Figure 2.10

General Register Data Formats..........................................................................

Figure 2.11

Memory Data Formats.......................................................................................

Figure 2.12

Instruction Formats (Examples) ........................................................................

Figure 2.13

Branch Address Specification in Memory Indirect Mode .................................

Figure 2.14

Processing States ...............................................................................................

Figure 2.15

State Transitions ................................................................................................

Figure 2.16

Stack Structure after Exception Handling (Examples) ......................................

Figure 2.17

On-Chip Memory Access Cycle ........................................................................

Figure 2.18

Pin States during On-Chip Memory Access ......................................................

Figure 2.19

On-Chip Supporting Module Access Cycle.......................................................

Figure 2.20

Pin States during On-Chip Supporting Module Access.....................................

Section 3 MCU Operating Modes

Figure 3.1

H8S/2138 (Except for F-ZTAT A-Mask Version) and H8S/2134 Memory Map

in Each Operating Mode....................................................................................

Figure 3.2

H8S/2138 F-ZTAT A-Mask Version Memory Map in Each Operating Mode

Figure 3.3

H8S/2133 Memory Map in Each Operating Mode............................................

Figure 3.4

H8S/2137 and H8S/2132 Memory Map in Each Operating Mode ....................

Figure 3.5

H8S/2130 Memory Map in Each Operating Mode............................................

Section 4 Exception Handling

Figure 4.1

Exception Sources .............................................................................................

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