HD6432138SW datasheet(31/1061 Pages) RENESAS

31 / 1061 page

Rev. 4.00 Jun 06, 2006 page xxxi of liv

22.7.1 Program Mode ..................................................................................................... 646

22.7.2 Program-Verify Mode.......................................................................................... 647

22.7.3 Erase Mode .......................................................................................................... 649

22.7.4 Erase-Verify Mode .............................................................................................. 649

22.8

Flash Memory Protection.................................................................................................. 651

22.8.1 Hardware Protection ............................................................................................ 651

22.8.2 Software Protection.............................................................................................. 651

22.8.3 Error Protection.................................................................................................... 652

22.9

Interrupt Handling when Programming/Erasing Flash Memory....................................... 654

22.10 Flash Memory Programmer Mode .................................................................................... 655

22.10.1 Programmer Mode Setting ................................................................................... 655

22.10.2 Socket Adapters and Memory Map ..................................................................... 656

22.10.3 Programmer Mode Operation .............................................................................. 656

22.10.4 Memory Read Mode ............................................................................................ 657

22.10.5 Auto-Program Mode ............................................................................................ 661

22.10.6 Auto-Erase Mode ................................................................................................. 663

22.10.7 Status Read Mode ................................................................................................ 664

22.10.8 Status Polling ....................................................................................................... 666

22.10.9 Programmer Mode Transition Time .................................................................... 666

22.10.10 Notes on Memory Programming...................................................................... 667

22.11 Flash Memory Programming and Erasing Precautions ..................................................... 667

22.12 Note on Switching from F-ZTAT Version to Mask ROM Version .................................. 668

Section 23 Clock Pulse Generator .................................................................................. 669

23.1

Overview........................................................................................................................... 669

23.1.1 Block Diagram ..................................................................................................... 669

23.1.2 Register Configuration......................................................................................... 670

23.2

Register Descriptions ........................................................................................................ 670

23.2.1 Standby Control Register (SBYCR) .................................................................... 670

23.2.2 Low-Power Control Register (LPWRCR) ........................................................... 671

23.3

Oscillator........................................................................................................................... 672

23.3.1 Connecting a Crystal Resonator........................................................................... 672

23.3.2 External Clock Input ............................................................................................ 674

23.4

Duty Adjustment Circuit ................................................................................................... 677

23.5

Medium-Speed Clock Divider .......................................................................................... 677

23.6

Bus Master Clock Selection Circuit .................................................................................. 677

23.7

Subclock Input Circuit ...................................................................................................... 677

23.8

Subclock Waveform Shaping Circuit................................................................................ 678

23.9

Clock Selection Circuit ..................................................................................................... 679

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