HD6432138SW datasheet(14/1061 Pages) RENESAS

14 / 1061 page

Rev. 4.00 Jun 06, 2006 page xiv of liv

Item

Page

Revision (See Manual for Details)

B.3 Function

938

STCR H'FFC3 System

Figure amended

—

R/W

IICX1

R/W

IICX0

R/W

IICE

R/W

FLSHE

R/W

ICKS0

R/W

—

R/W

ICKS1

R/W

Bit

Initial value

Read/Write

Internal Clock Source

Select 1 and 0*1

Reserved

Flash memory control register enable

Flash memory control register not selected

Flash memory control register selected

I2C master enable

CPU access to SCI0, SCI1, and SCI2 control

registers is enabled

CPU access to I2C bus interface data, PWMX data

registers and control registers is enabled

I2C transfer select 1 and 0*2

Reserved

939

SYSCR H'FFC4 System

Figure amended

CS2E

R/W

IOSE

R/W

INTM1

INTM0

R/W

XRST

RAME

R/W

NMIEG

R/W

HIE

R/W

Bit

Initial value

Read/Write

RAM Enable

On-chip RAM is disabled

On-chip RAM is enabled

Host interface enable

Addresses H'(FF)FFF0 to H'(FF)FFF7

and H'(FF)FFFC to H'(FF)FFFF are

used for access to 8-bit timer (channel

X and Y) data registers and control

registers, and timer connection

control registers

Addresses H'(FF)FFF0 to H'(FF)FFF7

and H'(FF)FFFC to H'(FF)FFFF are

used for access to host interface data

registers and control registers, and

keyboard controller and MOS input

pull-up control registers

NMI edge select

Falling edge

Rising edge

External reset

Reset generated by watchdog timer overflow

Reset generated by an external reset

Interrupt control selection mode 1 and 0

INTM1

Bit 5

Interrupts controlled by I bit

(Initial value)

Interrupts controlled by I and UI bits, and ICR

Cannot be used in the LSI

INTM0

Bit 4

Interrupt

control mode

Description

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