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HD6432138SW Scheda tecnica(PDF) 51 Page - Renesas Technology Corp

Il numero della parte HD6432138SW
Spiegazioni elettronici  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1061 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6432138SW Scheda tecnica(HTML) 51 Page - Renesas Technology Corp

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Rev. 4.00 Jun 06, 2006 page li of liv
Table 21.20 Status Polling Output Truth Table.......................................................................... 620
Table 21.21 Command Wait State Transition Time Specifications ........................................... 620
Table 21.22 Registers Present in F-ZTAT Version but Absent in Mask ROM Version ............ 622
Section 22 ROM (H8S/2138 F-ZTAT A-Mask Version,
H8S/2134 F-ZTAT A-Mask Version)
Table 22.1
ROM Register ........................................................................................................ 624
Table 22.2
Operating Modes and ROM ................................................................................... 625
Table 22.3
Flash Memory Pins................................................................................................. 632
Table 22.4
Flash Memory Registers......................................................................................... 632
Table 22.5
Flash Memory Erase Blocks................................................................................... 638
Table 22.6
Setting On-Board Programming Modes ................................................................. 639
Table 22.7
System Clock Frequencies for which Automatic Adjustment of the Chip's Bit
Rate Is Possible ...................................................................................................... 642
Table 22.8
Hardware Protection............................................................................................... 651
Table 22.9
Software Protection ................................................................................................ 652
Table 22.10 Programmer Mode Pin Settings ............................................................................. 655
Table 22.11 Settings for Each Operating Mode in Programmer Mode ...................................... 657
Table 22.12 Programmer Mode Commands .............................................................................. 657
Table 22.13 AC Characteristics in Memory Read Mode ........................................................... 658
Table 22.14 AC Characteristics when Entering Another Mode from Memory Read Mode ...... 659
Table 22.15 AC Characteristics in Memory Read Mode ........................................................... 660
Table 22.16 AC Characteristics in Auto-Program Mode ........................................................... 661
Table 22.17 AC Characteristics in Auto-Erase Mode ................................................................ 663
Table 22.18 AC Characteristics in Status Read Mode ............................................................... 664
Table 22.19 Status Read Mode Return Commands.................................................................... 665
Table 22.20 Status Polling Output Truth Table.......................................................................... 666
Table 22.21 Command Wait State Transition Time Specifications ........................................... 666
Table 22.22 Registers Present in F-ZTAT Version but Absent in Mask ROM Version ............ 668
Section 23 Clock Pulse Generator
Table 23.1
CPG Registers ........................................................................................................ 670
Table 23.2
Damping Resistance Value .................................................................................... 672
Table 23.3
Crystal Resonator Parameters ................................................................................ 673
Table 23.4
External Clock Input Conditions ............................................................................ 675
Table 23.5
External Clock Output Settling Delay Time........................................................... 676
Table 23.6
Subclock Input Conditions ..................................................................................... 677
Section 24 Power-Down State
Table 24.1
H8S/2138 Group and H8S/2134 Group Internal States in Each Mode .................. 682
Table 24.2
Power-Down Mode Transition Conditions............................................................. 684



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