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HD6432138SW Scheda tecnica(PDF) 46 Page - Renesas Technology Corp |
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HD6432138SW Scheda tecnica(HTML) 46 Page - Renesas Technology Corp |
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46 / 1061 page ![]() Rev. 4.00 Jun 06, 2006 page xlvi of liv Tables Section 1 Overview Table 1.1 Overview ................................................................................................................ 2 Table 1.2 H8S/2138 Group Pin Functions in Each Operating Mode ..................................... 11 Table 1.3 H8S/2134 Group Pin Functions in Each Operating Mode ..................................... 15 Table 1.4 Pin Functions..........................................................................................................18 Section 2 CPU Table 2.1 Instruction Classification........................................................................................ 42 Table 2.2 Combinations of Instructions and Addressing Modes............................................ 43 Table 2.3 Instructions Classified by Function ........................................................................ 45 Table 2.4 Addressing Modes.................................................................................................. 55 Table 2.5 Absolute Address Access Ranges .......................................................................... 56 Table 2.6 Effective Address Calculation................................................................................ 59 Table 2.7 Exception Handling Types and Priority ................................................................. 64 Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Selection............................................................................ 71 Table 3.2 MCU Registers ....................................................................................................... 72 Table 3.3 Pin Functions in Each Mode .................................................................................. 79 Section 4 Exception Handling Table 4.1 Exception Types and Priority ................................................................................. 91 Table 4.2 Exception Vector Table.......................................................................................... 93 Table 4.3 Status of CCR and EXR after Trap Instruction Exception Handling ..................... 98 Section 5 Interrupt Controller Table 5.1 Interrupt Controller Pins......................................................................................... 102 Table 5.2 Interrupt Controller Registers................................................................................. 103 Table 5.3 Correspondence between Interrupt Sources and ICR Settings ............................... 105 Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities ................................ 116 Table 5.5 Interrupt Control Modes......................................................................................... 121 Table 5.6 Interrupts Selected in Each Interrupt Control Mode .............................................. 123 Table 5.7 Operations and Control Signal Functions in Each Interrupt Control Mode ........... 123 Table 5.8 Interrupt Response Times....................................................................................... 131 Table 5.9 Number of States in Interrupt Handling Routine Execution .................................. 131 Table 5.10 Interrupt Source Selection and Clearing Control ................................................... 135 |
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