HD6432138SW datasheet(38/1061 Pages) RENESAS

38 / 1061 page

Rev. 4.00 Jun 06, 2006 page xxxviii of liv

Figure 10.4 (3) Output Waveform.............................................................................................. 268

Figure 10.4 (4) Output Waveform.............................................................................................. 268

Section 11 16-Bit Free-Running Timer

Figure 11.1

Block Diagram of 16-Bit Free-Running Timer ................................................. 270

Figure 11.2

Input Capture Buffering (Example)................................................................... 274

Figure 11.3

Increment Timing with Internal Clock Source .................................................. 287

Figure 11.4

Increment Timing with External Clock Source ................................................. 288

Figure 11.5

Timing of Output Compare A Output ............................................................... 288

Figure 11.6

Clearing of FRC by Compare-Match A............................................................. 289

Figure 11.7

Input Capture Signal Timing (Usual Case)........................................................ 289

Figure 11.8

Input Capture Signal Timing

(Input Capture Input When ICRA/B/C/D Is Read)............................................ 290

Figure 11.9

Buffered Input Capture Timing (Usual Case).................................................... 290

Figure 11.10

Buffered Input Capture Timing

(Input Capture Input When ICRA or ICRC Is Read) ........................................ 291

Figure 11.11

Setting of Input Capture Flag (ICFA to ICFD).................................................. 292

Figure 11.12

Setting of Output Compare Flag (OCFA, OCFB) ............................................. 293

Figure 11.13

Setting of Overflow Flag (OVF)........................................................................ 294

Figure 11.14

OCRA Automatic Addition Timing .................................................................. 294

Figure 11.15

Input Capture Mask Signal Setting Timing ....................................................... 295

Figure 11.16

Input Capture Mask Signal Clearing Timing..................................................... 295

Figure 11.17

Pulse Output (Example) .................................................................................... 297

Figure 11.18

FRC Write-Clear Contention............................................................................. 298

Figure 11.19

FRC Write-Increment Contention ..................................................................... 299

Figure 11.20

Contention between OCR Write and Compare-Match

(When Automatic Addition Function Is Not Used)........................................... 300

Figure 11.21

Contention between OCRAR/OCRAF Write and Compare-Match

(When Automatic Addition Function Is Used).................................................. 301

Section 12 8-Bit Timers

Figure 12.1

Block Diagram of 8-Bit Timer Module ............................................................. 306

Figure 12.2

Count Timing for Internal Clock Input.............................................................. 325

Figure 12.3

Count Timing for External Clock Input............................................................. 326

Figure 12.4

Timing of CMF Setting ..................................................................................... 326

Figure 12.5

Timing of Timer Output .................................................................................... 327

Figure 12.6

Timing of Compare-Match Clear ...................................................................... 327

Figure 12.7

Timing of Clearing by External Reset Input...................................................... 328

Figure 12.8

Timing of OVF Setting...................................................................................... 328

Figure 12.9

Timing of Input Capture Operation ................................................................... 330

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