HD6432138SW datasheet(535/1061 Pages) RENESAS

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Section 16 I

2C Bus Interface [H8S/2138 Group Option]

Rev. 4.00 Jun 06, 2006 page 481 of 1004

REJ09B0301-0400

Bits 6 and 5—I

2C Transfer Select 1 and 0 (IICX1, IICX0): These bits, together with bits CKS2

to CKS0 in ICMR of IIC1, select the transfer rate in master mode. For details, see section 16.2.4,

2C Bus Mode Register (ICMR).

Bit 4—I

2C Master Enable (IICE): Controls CPU access to the I2C bus interface data and control

registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR).

Bit 4

IICE

Description

CPU access to I

2C bus interface data and control registers is disabled

(Initial value)

CPU access to I

2C bus interface data and control registers is enabled

Bit 3—Flash Memory Control Register Enable (FLSHE): Controls the operation of the flash

memory in F-ZTAT versions. For details, see section 21, ROM (Mask ROM Version, H8S/2138

F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT), and section 22, ROM (H8S/2138 F-ZTAT

A-Mask Version, H8S/2134 F-ZTAT A-Mask Version).

Bit 2—Reserved: Do not write 1 to this bit.

Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): These bits, together with

bits CKS2 to CKS0 in TCR, select the clock input to the timer counters (TCNT). For details, see

section 12.2.4, Timer Control Register (TCR).

16.2.8

DDC Switch Register (DDCSWR)

Bit

Initial value

Read/Write

Notes: 1. Only 0 can be written, to clear the flag.

2. Always read as 1.

SWE

R/W

R/(W)*1

CLR3

W*2

CLR0

W*2

CLR2

W*2

CLR1

W*2

DDCSWR is an 8-bit readable/writable register that controls the IIC channel 0 automatic format

switching function.

DDCSWR is initialized to H'0F by a reset and in hardware standby mode.

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