HD6432138SW datasheet(580/1061 Pages) RENESAS

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Section 17 Host Interface [H8S/2138 Group]

Rev. 4.00 Jun 06, 2006 page 526 of 1004

REJ09B0301-0400

17.1.4

Table 17.2 lists the host interface registers. Host interface registers HICR, IDR1, IDR2, ODR1,

ODR2, STR1, and STR2 can only be accessed when the HIE bit is set to 1 in SYSCR.

Table 17.2

Host Interface Registers

R/W

Master Address*

Name

Abbreviation

Slave

Host

Initial

Value

Slave

Address*

CS1

CS2

HA0

System control

SYSCR

R/W*

—

H'09

H'FFC4

—

System control

SYSCR2

R/W

—

H'00

H'FF83

—

Host interface

control register

HICR

R/W

—

H'F8

H'FFF0

—

Input data

IDR1

—

H'FFF4

0/1*

Output data

ODR1

R/W

—

H'FFF5

Status register 1

STR1

R/(W)*

H'00

H'FFF6

Input data

IDR2

—

H'FFFC

0/1*

Output data

ODR2

R/W

—

H'FFFD

Status register 2

STR2

R/(W)*

H'00

H'FFFE

MSTPCRH

R/W

—

H'3F

H'FF86

—

Module stop

control register

MSTPCRL

R/W

—

H'FF

H'FF87

—

Notes: 1. Bits 5 and 3 are read-only bits.

2. The user-defined bits (bits 7 to 4 and 2) are read/write accessible from the slave

processor.

3. Address when accessed from the slave processor. The lower 16 bits of the address are

shown.

4. Pin inputs used in access from the host processor.

5. The HA0 input discriminates between writing of commands and data.

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