HD6432138SW datasheet(588/1061 Pages) RENESAS

Il numero della parte	HD6432138SW

Spiegazioni elettronici	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1061 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Section 17 Host Interface [H8S/2138 Group]

Rev. 4.00 Jun 06, 2006 page 534 of 1004

REJ09B0301-0400

Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR2. This bit is an

internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads

IDR2.

The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For

details see table 17.8, Fast A20 Gate Output Signals.

Bit 1

IBF

Description

[Clearing condition]

When the slave processor reads IDR2

(Initial value)

[Setting condition]

When the host processor writes to IDR2

Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR2. Cleared to

0 when the host processor reads ODR2. The IBF flag setting and clearing conditions are different

when the fast A20 gate is used. For details see table 17.8, Fast A20 Gate Output Signals.

Bit 0

OBF

Description

[Clearing condition]

When the host processor reads ODR2 or the slave writes 0 in the OBF bit

(Initial value)

[Setting condition]

When the slave processor writes to ODR2

Table 17.4 shows the conditions for setting and clearing the STR2 flags.

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