HD6432138SW datasheet(916/1061 Pages) RENESAS

Il numero della parte	HD6432138SW

Spiegazioni elettronici	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1061 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

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Appendix A Instruction Set

Rev. 4.00 Jun 06, 2006 page 862 of 1004

REJ09B0301-0400

A.5

Bus States during Instruction Execution

Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See

table A.4 for the number of states per cycle.

How to Read the Table:

Instruction

JMP@aa:24

R:W 2nd

Internal

operation,

2 state

R:W EA

End of instruction

Order of execution

Read effective address (word-size read)

No read or write

Read 2nd word of current instruction

(word-size read)

Legend:

R:B

Byte-size read

R:W

Word-size read

W:B

Byte-size write

W:W

Word-size write

Transfer of the bus is not performed immediately after this cycle

2nd

Address of 2nd word (3rd and 4th bytes)

3rd

Address of 3rd word (5th and 6th bytes)

4th

Address of 4th word (7th and 8th bytes)

5th

Address of 5th word (9th and 10th bytes)

Start address of instruction following executing instruction

Effective address

VEC

Vector address

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