HD6432138SW datasheet(108/1061 Pages) RENESAS

Il numero della parte	HD6432138SW

Spiegazioni elettronici	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1061 Pages

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Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

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108 / 1061 page

Section 2 CPU

Rev. 4.00 Jun 06, 2006 page 54 of 1004

REJ09B0301-0400

Figure 2.12 shows examples of instruction formats.

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm, etc.

(1) Operation field only

(2) Operation field and register fields

(3) Operation field, register fields, and effective address extension

EA (disp)

(4) Operation field, effective address extension, and condition field

EA (disp)

BRA d:16, etc

Figure 2.12 Instruction Formats (Examples)

2.6.5

Notes on Use of Bit-Manipulation Instructions

The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit

manipulation, then write back the byte of data. Caution is therefore required when using these

instructions on a register containing write-only bits, or a port.

The BCLR instruction can be used to clear internal I/O register flags to 0. In this case, the relevant

flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt handling

routine, etc.

HD6432138SW Scheda tecnica(PDF) 108 Page - Renesas Technology Corp