HD6432138SW datasheet(146/1061 Pages) RENESAS

Il numero della parte	HD6432138SW

Spiegazioni elettronici	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Section 4 Exception Handling

Rev. 4.00 Jun 06, 2006 page 92 of 1004

REJ09B0301-0400

4.1.2

Exception Handling Operation

Exceptions originate from various sources. Trap instructions and interrupts are handled as follows:

1. The program counter (PC) and condition-code register (CCR) are pushed onto the stack.

2. The interrupt mask bits are updated. The T bit is cleared to 0.

3. A vector address corresponding to the exception source is generated, and program execution

starts from that address.

For a reset exception, steps 2 and 3 above are carried out.

4.1.3

Exception Sources and Vector Table

The exception sources are classified as shown in figure 4.1. Different vector addresses are

assigned to different exception sources.

Table 4.2 lists the exception sources and their vector addresses.

Exception

sources

Reset

Trace

Interrupts

Direct transition

Trap instruction

(Cannot be used in the H8S/2138 Group or H8S/2134 Group)

External interrupts: NMI, IRQ7 to IRQ0

Internal interrupts: interrupt sources in

on-chip supporting modules

Figure 4.1 Exception Sources

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