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HD6432138SW Scheda tecnica(PDF) 208 Page - Renesas Technology Corp |
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HD6432138SW Scheda tecnica(HTML) 208 Page - Renesas Technology Corp |
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208 / 1061 page ![]() Section 6 Bus Controller Rev. 4.00 Jun 06, 2006 page 154 of 1004 REJ09B0301-0400 T1 Address bus φ AS/IOS (IOSE = 0) Data bus T2 T3 T1 T2 T1 Full access T2 RD Burst access Only lower address changed Read data Read data Read data Figure 6.8 (a) Example of Burst ROM Access Timing (When AST = BRSTS1 = 1) T1 Address bus φ AS/IOS (IOSE = 0) Data bus T2 T1 T1 Full access RD Burst access Only lower address changed Read data Read data Read data Figure 6.8 (b) Example of Burst ROM Access Timing (When AST = BRSTS1 = 0) |
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