HD6432138SW datasheet(220/1061 Pages) RENESAS

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Section 7 Data Transfer Controller [H8S/2138 Group]

Rev. 4.00 Jun 06, 2006 page 166 of 1004

REJ09B0301-0400

7.2.6

DTC Transfer Count Register B (CRB)

76543210

Bit

Initial value

—

——

—

——

—

——

—

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Read/Write

CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in

block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1

every time data is transferred, and transfer ends when the count reaches H'0000.

7.2.7

DTC Enable Registers (DTCER)

DTCE7

R/W

DTCE6

R/W

DTCE5

R/W

DTCE4

R/W

DTCE3

R/W

DTCE0

R/W

DTCE2

R/W

DTCE1

R/W

Bit

Initial value

Read/Write

The DTC enable registers comprise five 8-bit readable/writable registers, DTCERA to DTCERE,

with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or

disable DTC service for the corresponding interrupt sources.

The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.

Bit n—DTC Activation Enable (DTCEn)

Bit n

DTCEn

Description

DTC activation by interrupt is disabled

(Initial value)

[Clearing conditions]

• When data transfer ends with the DISEL bit set to 1

• When the specified number of transfers end

DTC activation by interrupt is enabled

[Holding condition]

When the DISEL bit is 0 and the specified number of transfers have not ended

(n = 7 to 0)

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