Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

Preview PDF HTML

HD6432138SW Scheda tecnica(PDF) 311 Page - Renesas Technology Corp

Il numero della parte HD6432138SW
Spiegazioni elettronici  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1061 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6432138SW Scheda tecnica(HTML) 311 Page - Renesas Technology Corp

Back Button HD6432138SW Datasheet HTML 307Page - Renesas Technology Corp HD6432138SW Datasheet HTML 308Page - Renesas Technology Corp HD6432138SW Datasheet HTML 309Page - Renesas Technology Corp HD6432138SW Datasheet HTML 310Page - Renesas Technology Corp HD6432138SW Datasheet HTML 311Page - Renesas Technology Corp HD6432138SW Datasheet HTML 312Page - Renesas Technology Corp HD6432138SW Datasheet HTML 313Page - Renesas Technology Corp HD6432138SW Datasheet HTML 314Page - Renesas Technology Corp HD6432138SW Datasheet HTML 315Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 311 / 1061 page
background image
Section 10 14-Bit PWM D/A
Rev. 4.00 Jun 06, 2006 page 257 of 1004
REJ09B0301-0400
10.2.2
D/A Data Registers A and B (DADRA and DADRB)
15
13
DA13
1
R/W
14
12
DA12
1
R/W
13
11
DA11
1
R/W
12
10
DA10
1
R/W
11
9
DA9
1
R/W
8
6
DA6
1
R/W
10
8
DA8
1
R/W
9
7
DA7
1
R/W
Bit (CPU)
Bit (Data)
DADRA
Initial value
Read/Write
7
5
DA5
1
R/W
6
4
DA4
1
R/W
5
3
DA3
1
R/W
4
2
DA2
1
R/W
3
1
DA1
1
R/W
0
—
—
1
—
2
0
DA0
1
R/W
1
—
CFS
1
R/W
DADRH
DADRL
DA13
1
R/W
DA12
1
R/W
DA11
1
R/W
DA10
1
R/W
DA9
1
R/W
DA6
1
R/W
DA8
1
R/W
DA7
1
R/W
DADRB
Initial value
Read/Write
DA5
1
R/W
DA4
1
R/W
DA3
1
R/W
DA2
1
R/W
DA1
1
R/W
REGS
1
R/W
DA0
1
R/W
CFS
1
R/W
There are two 16-bit readable/writable D/A data registers: DADRA and DADRB. DADRA
corresponds to PWM D/A channel A, and DADRB to PWM D/A channel B. The CPU can read
and write the PWM D/A data register values, but since DADRA and DADRB are 16-bit registers,
data transfers between them and the CPU are performed using a temporary register (TEMP). See
section 10.3, Bus Master Interface, for details.
The least significant (CPU) bit of DADRA is not used and is always read as 1.
DADR is initialized to H'FFFF by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Scheda tecnica Scarica

Go To PDF Page


Link URL



Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   Collegamento alla scheda tecnica    |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com