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H8S/2218 Scheda tecnica(PDF) 365 Page - Renesas Technology Corp |
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H8S/2218 Scheda tecnica(HTML) 365 Page - Renesas Technology Corp |
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365 / 750 page ![]() Section 9 16-Bit Timer Pulse Unit (TPU) Rev.6.00 Jun. 03, 2008 Page 317 of 698 REJ09B0074-0600 9.5.5 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 9.19 shows the correspondence between external clock pins and channels. Table 9.19 Phase Counting Mode Clock Input Pins External Clock Pins Channels A-Phase B-Phase When channel 1 is set to phase counting mode TCLKA TCLKB When channel 2 is set to phase counting mode TCLKC TCLKD Example of Phase Counting Mode Setting Procedure: Figure 9.25 shows an example of the phase counting mode setting procedure. Phase counting mode Select phase counting mode Start count <Phase counting mode> Select phase counting mode with bits MD3 to MD0 in TMDR. Set the CST bit in TSTR to 1 to start the count operation. [1] [2] [1] [2] Figure 9.25 Example of Phase Counting Mode Setting Procedure |
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