H8SSLASH2218 datasheet(389/750 Pages) RENESAS

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Section 10 Watchdog Timer (WDT)

Rev.6.00 Jun. 03, 2008 Page 341 of 698

REJ09B0074-0600

Bit

Bit Name

Initial Value

R/W

Description

OVF

R/(W)*

Overflow Flag

Indicates that TCNT has overflowed. Only a write of

0 is permitted, to clear the flag.

[Setting condition]

When TCNT overflows (changes from H'FF to H'00)

When internal reset request generation is selected

in watchdog timer mode, OVF is cleared

automatically by the internal reset.

[Clearing condition]

Cleared by reading TCSR when OVF = 1, then

writing 0 to OVF

When polling CVF when the interval timer interrupt

has been prohibited, OVF = 1 status should be read

two or more times.

WT/

R/W

Timer Mode Select

Selects whether the WDT is used as a watchdog

timer or interval timer.

0: Interval timer mode

1: Watchdog timer mode

TME

R/W

Timer Enable

When this bit is set to 1, TCNT starts counting.

When this bit is cleared, TCNT stops counting and

is initialized to H'00.

4, 3

—

All 1

—

Reserved

These bits are always read as 1 and cannot be

modified.

CKS2

CKS1

CKS0

R/W

Clock Select 0 to 2

Selects the clock source to be input to TCNT. The

overflow frequency for

φ = 16 MHz is enclosed in

parentheses. The overflow period is the time from

when TCNT starts counting up from H'00 until

overflow occurs.

000: Clock

φ/2 (frequency: 32.0 μs)

001: Clock

φ/64 (frequency: 1.0 ms)

010: Clock

φ/128 (frequency: 2.0 ms)

011: Clock

φ/512 (frequency: 8.2 ms)

100: Clock

φ/2048 (frequency: 32.8 ms)

101: Clock

φ/8192 (frequency: 131.1 ms)

110: Clock

φ/32768 (frequency: 524.3 ms)

111: Clock

φ/131072 (frequency: 2.1 s)

Note: * The write value should always be 0 to clear this flag.

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