H8SSLASH2218 datasheet(530/750 Pages) RENESAS

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Section 14 Universal Serial Bus (USB)

Rev.6.00 Jun. 03, 2008 Page 482 of 698

REJ09B0074-0600

14.3.17

USB Interrupt Flag Register 1 (UIFR1)

UIFR1 is an interrupt flag register indicating the EP1 and EP2 status. If the corresponding bit is set

to 1, the corresponding

EXIRQ0 or EXIRQ1 interrupt is requested to the CPU. EP1TR flags can

be cleared by writing 0 to them. Writing 1 to them is invalid and causes no operation.

Consequently, to clear a flag, write 0 to the corresponding bit and 1 to all the other bits. (For

example, write H'FD to clear bit 1.) The bit-clear instruction is a read/modify/write instruction, so

if a new flag is set between the read and write operations, there is a danger that it may be cleared

erroneously. Therefore, do not use the bit-clear instruction to clear bits in this interrupt flag

resister. However, EP1EMPTY, EP2READY, and EP1ALLEMPTYs are status bits to indicate the

EP1, EP2, and FIFO state respectively, and cannot be cleared.

Bit

Bit Name

Initial Value

R/W

Description

7 to 4 —

All 0

Reserved

These bits are always read as 0 and cannot be

modified.

EP1ALL

EMPTYs

EP1 FIFO All Empty Status

EP1 FIFO has a dual-FIFO configuration. This bit is set

to 1 if there is no valid data in both FIFOs. This

corresponds to the negative-electrode signal for the

EP1DE bit in UDSR.

An interrupt cannot be required by EP1ALLEMPTY.

EP2READY 0

EP2 Data Ready

EP2 FIFO has a dual-FIFO configuration. This bit is set

to 1 if there is valid data at least in either of FIFOs.

This bit is cleared to 0 if there is no valid data in both

FIFOs. This bit is a status bit and cannot be cleared.

The corresponding interrupt output is

EXIRQ0 or

EXIRQ1.

EP1TR

R/(W)* EP1 Transfer Request

Set to 1 if there is no valid data in both FIFOs when an

IN token is sent from the host to EP1. The

corresponding interrupt output is

EXIRQ0 or EXIRQ1.

EP1EMPTY 1

EP1 FIFO Empty

EP1 FIFO has a dual-FIFO configuration. This bit is set

to 1 if there is no valid data at least in either of FIFOs.

This bit is cleared to 0 if there is valid data in both

FIFOs. This bit is a status bit and cannot be cleared.

The corresponding interrupt output is

EXIRQ0 or

EXIRQ1.

Note:* The write value should always be 0 to clear this flag.

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