H8SSLASH2218 datasheet(533/750 Pages) RENESAS

533 / 750 page

Section 14 Universal Serial Bus (USB)

Rev.6.00 Jun. 03, 2008 Page 485 of 698

REJ09B0074-0600

14.3.20

USB Interrupt Enable Register 1 (UIER1)

UIER1 enables the interrupt request indicated in the interrupt flag register 1 (UIFR1). When an

interrupt flag is set while the corresponding bit in UIER1 is set to 1, an interrupt is requested by

asserting the corresponding

EXIRQ0 or EXIRQ1. Either EXIRQ0 or EXIRQ1 must be selected by

the interrupt select register 1 (UISR1).

Bit

Bit Name

Initial Value

R/W

Description

7 to 4 —

All 0

Reserved

These bits are always read as 0.

—

R/W

Reserved

The write value should always be 0.

EP2READYE 0

R/W

Enables the EP2READY interrupt.

EP1TRE

R/W

Enables the EP1TR interrupt.

EP1EMPTYE 0

R/W

Enables the EP1EMPTYE interrupt.

14.3.21

USB Interrupt Enable Register 3 (UIER3)

UIER3 enables the interrupt request indicated in the interrupt flag register 3 (UIFR3). This register

is readable/writable while the USB module stop 2 bit (MSTPB0) in MSTPCRB is 1.

When an interrupt flag is set while the corresponding bit in UIER3 is set to 1, an interrupt is

requested by asserting the corresponding

EXIRQ0 or EXIRQ1. Either EXIRQ0 or EXIRQ1 must

be selected by the interrupt select register 3 (UISR3). Note, however, that the SPRSiE bit is an

interrupt enable bit specific to the

IRQ6 pin and cannot be selected by UISR3.

Bit

Bit Name

Initial Value

R/W

Description

CK48READYE 1

R/W

Enables the CK48READY interrupt.

SOFE

R/W

Enables the SOF interrupt.

SETCE

R/W

Enables the SETC interrupt.

4, 3

—

All 0

Reserved

These bits are always read as 0.

SPRSiE

R/W

Enables the SPRSi interrupt. (only for

IRQ6)

—

Reserved

This bit is always read as 0.

VBUSiE

R/W

Enables the VBUSi interrupt.

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