H8SSLASH2218 datasheet(631/750 Pages) RENESAS

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Section 17 Flash Memory (F-ZTAT Version)

Rev.6.00 Jun. 03, 2008 Page 583 of 698

REJ09B0074-0600

17.9

Program/Erase Protection

There are three kinds of flash memory program/erase protection: hardware protection, software

protection, and error protection.

17.9.1

Hardware Protection

Hardware protection refers to a state in which programming/erasing of flash memory is forcibly

disabled or aborted because of a transition to reset or standby mode. Flash memory control

and erase block register 2 (EBR2) are initialized. In a reset via the

RES pin, the reset state is not

entered unless the

RES pin is held low until oscillation stabilizes after powering on. In the case of

a reset during operation, hold the

RES pin low for the RES pulse width specified in the AC

Characteristics section.

17.9.2

Software Protection

Software protection can be implemented against programming/erasing of all flash memory blocks

by clearing the SWE1 bit in FLMCR1. When software protection is in effect, setting the P1 or E1

bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase

block register 1 (EBR1), and erase block register 2 (EBR2), erase protection can be set for

individual blocks. When EBR1 and EBR2 are set to H'00, erase protection is set for all blocks.

17.9.3

Error Protection

In error protection, an error is detected when the CPU's runaway occurs during flash memory

programming/erasing, or operation is not performed in accordance with the program/erase

algorithm, and the program/erase operation is aborted. Aborting the program/erase operation

prevents damage to the flash memory due to overprogramming or overerasing.

When the following errors are detected during programming/erasing of flash memory, the FLER

bit in FLMCR2 is set to 1, and the error protection state is entered.

Setting Conditions of FLER Bit (Erase Protection)

• When the flash memory of the relevant address area is read during programming/erasing

(including vector read and instruction fetch)

• Immediately after exception handling (excluding a reset) during programming/erasing

• When a SLEEP instruction is executed during programming/erasing

• When the CPU releases the bus mastership to the DMAC during programming/erasing

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