H8SSLASH2218 datasheet(672/750 Pages) RENESAS

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Section 20 Power-Down Modes

Rev.6.00 Jun. 03, 2008 Page 624 of 698

REJ09B0074-0600

20.7

Watch Mode

20.7.1

Transition to Watch Mode

CPU operation makes a transition to watch mode when the SLEEP instruction is executed in high-

speed mode or subactive mode with SBYCR SSBY=1, LPWRCR DTON = 0, and TCSR_1

PSS = 1.

In watch mode, the CPU is stopped and peripheral modules other than RTC are also stopped. The

contents of the CPU’s internal registers, the data in internal RAM, and the statuses of the internal

peripheral modules (excluding the A/D converter) and I/O ports are retained. To make a transition

to watch mode, bits SCK2 to SCK0 in SCKCR must be set to 0.

20.7.2

Exiting Watch Mode

Watch mode is exited by any interrupt (WOVI interrupt, NMI pin, or

IRQ0, to IRQ7), or signals at

the

RES, MRES*, or STBY pin.

• Exiting Watch Mode by Interrupts

When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or

medium-speed mode when the LPWRCR LSON bit = 0 or to subactive mode when the LSON

bit = 1. When a transition is made to high-speed mode, a stable clock is supplied to all LSI

circuits and interrupt exception processing starts after the time set in SBYCR STS2 to STS0

has elapsed. In case of IRQ0, to IRQ7 interrupts, no transition is made from watch mode if the

corresponding enable bit/pin function switching bit has been cleared to 0, and, in the case of

interrupts from the internal peripheral modules, the interrupt enable register has been set to

disable the reception of that interrupt, or is masked by the CPU.

See section 20.4.3, Setting Oscillation Stablization Time after Clearing Software Standby

Mode, for how to set the oscillation settling time when making a transition from watch mode to

high-speed mode.

• Exiting Watch Mode by RES or MRES* pin

For exiting watch mode by the

RES or MRES* pin, see section 20.4.2, Clearing Software

Standby Mode.

• Exiting Watch Mode by STBY pin

When the

STBY pin level is driven low, a transition is made to hardware standby mode.

Note:

* Supported only by the H8S/2218 Group.

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