H8SSLASH2218 datasheet(676/750 Pages) RENESAS

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Section 20 Power-Down Modes

Rev.6.00 Jun. 03, 2008 Page 628 of 698

REJ09B0074-0600

20.12

Usage Notes

20.12.1

I/O Port Status

In software standby mode or watch mode, I/O port states are retained. In addition, if the OPE bit is

set to 1, the address bus and bus control signal output are retained. Therefore, there is no reduction

in current dissipation for the output current when a high-level signal is output.

20.12.2

Current Dissipation during Oscillation Stabilization Wait Period

Current dissipation increases during the oscillation stabilization wait period.

20.12.3

Flash Memory Module Stop

Setting of the flash memory module stop mode should be carried out while the programs in the on-

chip RAM and external memory are executed. For details, see section 20.1.3, Module Stop Control

Registers A to C (MSTPCRA to MSTPCRC).

20.12.4

DMAC Module Stop

Depending on the operating status of the DMAC, the MSTPA7 bit may not be set to 1. Setting of

the DMAC module stop mode should be carried out only when the DMAC is not activated.

For details, section 7, DMA Controller (DMAC).

20.12.5

On-Chip Peripheral Module Interrupt

• Module stop mode

Relevant interrupt operations cannot be performed in module stop mode. Consequently, if

module stop mode is entered when an interrupt has been requested, it will not be possible to

clear the CPU interrupt source or DMAC activation source. Interrupts should therefore be

disabled before setting module stop mode.

• Subactive Mode/Watch Mode

On-chip peripheral modules (DMAC and TPU) that stop operation in subactive mode cannot

clear interrupts in subactive mode. Therefore, if subactive mode is entered when an interrupt is

requested, CPU interrupt factors cannot be cleared.

Interrupts should therefore before executing the SLEEP instruction and entering subactive or

watch mode.

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