H8SSLASH2218 datasheet(679/750 Pages) RENESAS

679 / 750 page

Section 21 List of Registers

Rev.6.00 Jun. 03, 2008 Page 631 of 698

REJ09B0074-0600

Section 21 List of Registers

The register list gives information on the on-chip I/O register addresses, how the register bits are

configured, and the register states in each operating mode. The information is given as shown

below.

1. Register Addresses (address order)

• Registers are listed from the lower allocation addresses.

• Registers are classified by functional modules.

• The access size is indicated.

2. Register Bits

• Bit configurations of the registers are described in the same order as the Register Addresses

(address order) above.

• Reserved bits are indicated by “⎯” in the bit name column.

• The bit number in the bit-name column indicates that the whole register is allocated as a

counter or for holding data.

• 16-bit or 24-bit registers are indicated from the bit on the MSB side.

3. Register States in Each Operating Mode

• Register states are described in the same order as the Register Addresses (address order) above.

• The register states described here are for the basic operating modes. If there is a specific reset

for an on-chip peripheral module, refer to the section on that on-chip peripheral module.

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