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H8S/2218 Scheda tecnica(PDF) 680 Page - Renesas Technology Corp |
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H8S/2218 Scheda tecnica(HTML) 680 Page - Renesas Technology Corp |
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680 / 750 page ![]() Section 21 List of Registers Rev.6.00 Jun. 03, 2008 Page 632 of 698 REJ09B0074-0600 21.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Register Name Abbreviation Number of Bits Address Data Bus Width Number of Access States Module USB reserved area ⎯ ⎯ H'C00000 to H'C0007F ⎯ ⎯ USB USB control register UCTLR 8 H'C00080 8 3 USB test register A UTSTRA 8 H'C00081 8 3 USB DMAC transfer request register UDMAR 8 H'C00082 8 3 USB device resume register UDRR 8 H'C00083 8 3 USB trigger register 0 UTRG0 8 H'C00084 8 3 USB FIFO clear register 0 UFCLR0 8 H'C00086 8 3 USB endpoint stall register 0 UESTL0 8 H'C00088 8 3 USB endpoint stall register 1 UESTL1 8 H'C00089 8 3 USB endpoint data register 0s UEDR0s 8 H'C00090 to H'C00093 8 3 USB endpoint data register 0i UEDR0i 8 H'C00094 to H'C00097 8 3 USB endpoint data register 0o UEDR0o 8 H'C00098 to H'C0009B 8 3 USB endpoint data register 3 UEDR3 8 H'C0009C to H'C0009F 8 3 USB endpoint data register 1 UEDR1 8 H'C000A0 to H'C000A3 8 3 USB endpoint data register 2 UEDR2 8 H'C000A4 to H'C000A7 8 3 |
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