H8SSLASH2218 datasheet(121/750 Pages) RENESAS

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Section 3 MCU Operating Modes

Rev.6.00 Jun. 03, 2008 Page 73 of 698

REJ09B0074-0600

Bit

Bit Name

Initial Value R/W

Description

–

R/W

Reserved

The write value should always be 0.

–

Reserved

This bit is always read as 0 and cannot be modified.

INTM1

INTM0

R/W

These bits select the control mode of the interrupt

controller. For details of the interrupt control modes,

see section 5.6, Interrupt Control Modes and Interrupt

Operation.

00: Interrupt control mode 0

01: Setting prohibited

10: Interrupt control mode 2

11: Setting prohibited

NMIEG

R/W

NMI Edge Select

Selects the valid edge of the NMI interrupt input.

0: An interrupt is requested at the falling edge of NMI

input

1: An interrupt is requested at the rising edge of NMI

input

MRESE

R/W

Manual Reset Select

Enables or disables the

MRES pin* input.

0: Manual reset is disabled

1: Manual reset is enabled

The

MRES input pin* can be used.

–

Reserved

This bit is always read as 0 and cannot be modified.

RAME

R/W

RAM Enable

Enables or disables the on-chip RAM. The RAME bit

is initialized when the reset status is released.

0: On-chip RAM is disabled

1: On-chip RAM is enabled

Note: * Supported only by the H8S/2218 Group.

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