H8SSLASH2218 datasheet(131/750 Pages) RENESAS

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Section 4 Exception Handling

Rev.6.00 Jun. 03, 2008 Page 83 of 698

REJ09B0074-0600

4.3

Reset

A reset has the highest exception priority.

When the

RES or MRES* pin goes low, all processing halts and this LSI enters the reset state. To

ensure that this LSI is reset, hold the

RES pin low for at least 20 ms at power-up or hold the RES

MRES* pin low for at least 20 states during operation.

A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules.

This LSI can also be reset by overflow of the watchdog timer. For details, see section 10,

Watchdog Timer (WDT).

Immediately after a reset, interrupt control mode 0 is set.

Notes:

TRST in the HD64F2218 and HD64F2218U, which incorporate a boundary scan function,

should be brought low when power is on. For details, see section 13, Boundary Scan

Function.

Supported only by the H8S/2218 Group.

4.3.1

Reset Types

A reset can be of either of two types for the H8S/2218 Group: a power-on reset or a manual reset.

A reset for the H8S/2212 Group is power-on reset. Reset types are shown in table 4.3. A power-on

reset should be used when powering on.

The internal state of the CPU is initialized by either type of reset. A power-on reset also initializes

all the registers in the on-chip peripheral modules, while a manual reset initializes all the registers

in the on-chip peripheral modules except for the bus controller and I/O ports, which retain their

previous states.

With a manual reset, since the on-chip peripheral modules are initialized, ports used as on-chip

peripheral module I/O pins are switched to I/O ports controlled by DDR and DR.

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