H8SSLASH2218 datasheet(135/750 Pages) RENESAS

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Section 4 Exception Handling

Rev.6.00 Jun. 03, 2008 Page 87 of 698

REJ09B0074-0600

4.4

Traces

Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control

mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5,

Interrupt Controller.

If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on

completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.4 shows

the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by

clearing the T bit in EXR to 0. The T bit saved on the stack retains its value of 1, and when control

is returned from the trace exception handling routine by the RTE instruction, trace mode resumes.

Trace exception handling is not carried out after execution of the RTE instruction.

Interrupts are accepted even within the trace exception handling routine.

Table 4.4

Status of CCR and EXR after Trace Exception Handling

CCR

EXR

Interrupt Control Mode

I2 to I0

Trace exception handling cannot be used.

–

Legend:

1: Set to 1

0: Cleared to 0

–: Retains value prior to execution.

4.5

Interrupts

Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt

control modes and can assign interrupts other than NMI to eight priority/mask levels to enable

multiplexed interrupt control. The source to start interrupt exception handling and the vector

address differ depending on the product. For details, refer to section 5, Interrupt Controller.

The interrupt exception handling is as follows:

1. The values in the program counter (PC), condition code register (CCR), and extended control

2. The interrupt mask bit is updated and the T bit is cleared.

3. A vector address corresponding to the interrupt source is generated, the start address is loaded

from the vector table to the PC, and program execution starts from that address.

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