H8SSLASH2218 datasheet(134/750 Pages) RENESAS

134 / 750 page

Section 4 Exception Handling

Rev.6.00 Jun. 03, 2008 Page 86 of 698

REJ09B0074-0600

(1) (3)

(2) (4)

(5)

(6)

: Reset exception handling vector address (for a power-on reset, (1) = H'000000, (3) = H'000002

for a manual reset, (1) = H'000004, (3) = H'000006)

: Start address (contents of reset exceptiion handling vector address)

: Start address ((5) = (2) (4))

: First program instruction

RES, MRES

Internal

Address bus

Internal

read signal

Internal

write signal

Internal

data bus

Vector

fetch

(1)

(3)

(5)

High

Internal

processing

Prefetch of first program

instruction

(4)

(6)

(2)

Figure 4.2 Reset Sequence (Modes 6 and 7)

4.3.3

Interrupts after Reset

If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and

CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,

including NMI, are disabled immediately after a reset. Since the first instruction of a program is

always executed immediately after the reset state ends, make sure that this instruction initializes

the stack pointer (example: MOV.L #xx: 32,SP).

4.3.4

State of On-Chip Peripheral Modules after Reset Release

After reset release, MSTPCRA, MSTPCRB, and MSTPCRC are initialized and all modules except

the DMAC enter module stop mode. Consequently, on-chip peripheral module registers cannot be

read from or written to. Register reading and writing is enabled when module stop mode is exited.

H8S/2218 Scheda tecnica(PDF) 134 Page - Renesas Technology Corp

H8S/2218 Scheda tecnica(HTML) 134 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL