H8SSLASH2218 datasheet(147/750 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.6.00 Jun. 03, 2008 Page 99 of 698

REJ09B0074-0600

5.4

Interrupt Sources

5.4.1

External Interrupts

There are seven external interrupts: NMI, IRQ7, and IRQ4 to IRQ0. These interrupts can be used

to restore this LSI from software standby mode. Though IRQ5 is only for the on-chip RTC and

IRQ6 is only for the on-chip USB, the interrupts can be used to restore this LSI from software

standby mode. IRQ5 and IRQ6 are functionally same as IRQ7 and IRQ4 to IRQ0.

NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU

regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG

bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling

edge on the NMI pin.

IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins

IRQ7

IRQ0. Interrupts IRQ7 to IRQ0 have the following features:

• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling

edge, rising edge, or both edges, at pins

IRQ7 to IRQ0

• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.

• The interrupt priority level can be set with IPR.

• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0

by software.

A block diagram of IRQn interrupts is shown in figure 5.2.

IRQnE

IRQnF

IRQn interrupt

request

Clear signal

Edge/level

detection circuit

IRQnSCA, IRQnSCB

IRQn input

Note: n = 7 to 0

Figure 5.2 Block Diagram of Interrupts IRQn

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