H8SSLASH2218 datasheet(144/750 Pages) RENESAS

144 / 750 page

Section 5 Interrupt Controller

Rev.6.00 Jun. 03, 2008 Page 96 of 698

REJ09B0074-0600

5.3.3

IRQ Sense Control Registers H and L (ISCRH, ISCRL)

The ISCR registers select the source that generates an interrupt request at pins

IRQ7 to IRQ0.

Bit

Bit Name

Initial Value

R/W

Description

IRQ7SCB

IRQ7SCA

R/W

IRQ7 Sense Control B

IRQ7 Sense Control A

00: Interrupt request generated at

IRQ7 input low level

01: Interrupt request generated at falling edge of

IRQ7

input

10: Interrupt request generated rising edge of

IRQ7

input

11: Interrupt request generated at both falling and

rising edges of

IRQ7 input

IRQ6SCB

IRQ6SCA

R/W

IRQ6*

1 Sense Control B

IRQ6*

1 Sense Control A

00: Setting prohibited when using on-chip USB

suspend or resume interrupt

01: Interrupt request generated at falling edge of

IRQ6

input

1x: Setting prohibited

IRQ5SCB

IRQ5SCA

R/W

IRQ5*

2 Sense Control B

IRQ5*

2 Sense Control A

00: Setting prohibited when using RTC interrupt

01: Interrupt request generated at falling edge of

IRQ5

input

1x: Setting prohibited

IRQ4SCB

IRQ4SCA

R/W

IRQ4 Sense Control B

IRQ4 Sense Control A

00: Interrupt request generated at

IRQ4 input low level

01: Interrupt request generated at falling edge of

IRQ4

input

10: Interrupt request generated at rising edge of

IRQ4

input

11: Interrupt request generated at both falling and

rising edges of

IRQ4 input

H8S/2218 Scheda tecnica(PDF) 144 Page - Renesas Technology Corp

H8S/2218 Scheda tecnica(HTML) 144 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL