H8SSLASH2218 datasheet(215/750 Pages) RENESAS

Il numero della parte	H8S/2218

Spiegazioni elettronici	16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

PDF	750 Pages

Scroll/Zoom	100%

Produttore elettronici	RENESAS [Renesas Technology Corp]

Homepage	http://www.renesas.com

Logo

215 / 750 page

Section 7 DMA Controller (DMAC)

Rev.6.00 Jun. 03, 2008 Page 167 of 698

REJ09B0074-0600

Bit Bit Name Initial Value

R/W

Description

⎯

All 0

R/W

Reserved

Although these bits are readable/writable, only 0 should be

written to.

• Full Address Mode (DMACRB)

Bit Bit Name Initial Value

R/W

Description

⎯

R/W

Reserved

Although this bit is readable/writable, only 0 should be written

to.

DAID

DAIDE

R/W

Destination Address Increment/Decrement

Destination Address Increment/Decrement Enable

These bits specify whether destination address register

MARB is to be incremented, decremented, or left unchanged,

when data transfer is performed.

00: MARB is fixed

01: MARB is incremented after a data transfer

• When DTSZ = 0, MARB is incremented by 1 after a

transfer

• When DTSZ = 1, MARB is incremented by 2 after a

transfer

10: MARB is fixed

11: MARB is decremented after a data transfer

• When DTSZ = 0, MARB is decremented by 1 after a

transfer

• When DTSZ = 1, MARB is decremented by 2 after a

transfer

⎯

R/W

Reserved

Although this bit is readable/writable, only 0 should be written

to.

H8S/2218 Scheda tecnica(PDF) 215 Page - Renesas Technology Corp

H8S/2218 Scheda tecnica(HTML) 215 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL