H8SSLASH2218 datasheet(226/750 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev.6.00 Jun. 03, 2008 Page 178 of 698

REJ09B0074-0600

7.4.2

Sequential Mode

Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode,

MAR is updated after each byte or word transfer in response to a single transfer request, and this is

executed the number of times specified in ETCR. One address is specified by MAR, and the other

by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.3

summarizes register functions in sequential mode.

Table 7.3

Function

DTDIR = 0

DTDIR = 1

Initial Setting

Operation

MAR

Source

address

Destination

address

Start address of

transfer destination

or transfer source

Incremented/

decremented every

transfer

IOAR

H'FF

Destination

address

Source

address

Start address of

transfer source or

transfer destination

Fixed

ETCR

Transfer counter

Number of transfers Decremented every

transfer, transfer

ends when count

reaches H'0000

MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is

incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the

lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Figure 7.2

illustrates operation in sequential mode.

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