H8SSLASH2218 datasheet(222/750 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev.6.00 Jun. 03, 2008 Page 174 of 698

REJ09B0074-0600

Bit Bit Name Initial Value

R/W

Description

–

R/W

Reserved

Although this bit is readable/writable, only 0 should be written

to.

Data Transfer Master Enable

Together with the DTE bit, this bit controls enabling or

disabling of data transfer on the relevant channel. When both

the DTME bit and the DTE bit are set to 1, transfer is enabled

for the channel. If the relevant channel is in the middle of a

burst mode transfer when an NMI interrupt is generated, the

DTME bit is cleared, the transfer is interrupted, and bus

mastership passes to the CPU. When the DTME bit is

subsequently set to 1 again, the interrupted transfer is

resumed. In block transfer mode, however, the DTME bit is

not cleared by an NMI interrupt, and transfer is not

interrupted.

The conditions for the DTME bit being cleared to 0 are as

follows:

• When initialization is performed

• When NMI is input in burst mode

• When 0 is written to the DTME bit

The condition for DTME being set to 1 is as follows:

• When 1 is written to DTME after DTME is read as 0

DTME1

R/W

Data Transfer Master Enable 1

Enables or disables data transfer on channel 1

0: Data transfer disabled. In burst mode, cleared to 0 by an

NMI interrupt

1: Data transfer enabled

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