AD9547SLASHPCBZ datasheet(53/104 Pages) AD

Il numero della parte	AD9547/PCBZ

Spiegazioni elettronici	Dual/Quad Input Network Clock Generator/Synchronizer

PDF	104 Pages

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Produttore elettronici	AD [Analog Devices]

Homepage	http://www.analog.com

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AD9547

Rev. 0 | Page 53 of 104

DATA BIT N – 1

DATA BIT N

SCLK

SDIO

SDO

tDV

Figure 54. Serial Control Port Timing—Read

SCLK DON'T CARE

DON'T CARE

16-BIT INSTRUCTION HEADER

SDIO

DON'T CARE

A0 A1

A5 A6

A9 A10 A11 A12

R/W

D5 D6

Figure 55. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data

SCLK

SDIO

tHIGH

tLOW

tCLK

tDS

tDH

BIT N

BIT N + 1

Figure 56. Serial Control Port Timing—Write

Table 33. Serial Control Port Timing

Parameter

Description

tDS

Setup time between data and the rising edge of SCLK

tDH

Hold time between data and the rising edge of SCLK

tCLK

Period of the clock

Setup time between the CS falling edge and SCLK rising edge (start of the communication cycle)

Setup time between the SCLK rising edge and CS rising edge (end of the communication cycle)

tHIGH

Minimum period that SCLK should be in a logic high state

tLOW

Minimum period that SCLK should be in a logic low state

tDV

SCLK to valid SDIO and SDO (see Figure 54)

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