AD9547SLASHPCBZ datasheet(9/104 Pages) AD

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AD9547

Rev. 0 | Page 9 of 104

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Rise/Fall Time1 (20% to 80%)

10 pF load

3.3 V Supply

Strong Drive Strength Setting

0.5

Weak Drive Strength Setting

14.5

1.8 V Supply

1.5

2.5

Duty Cycle

10 pF load

Output Voltage High (VOH)

Output driver static; strong drive

strength setting

AVDD3 = 3.3 V, IOH = 10 mA

2.6

AVDD3 = 3.3 V, IOH = 1 mA

2.9

AVDD3 = 1.8 V, IOH = 1 mA

1.5

Output Voltage Low (VOL)

Output driver static; strong drive

strength setting

AVDD3 = 3.3 V, IOL = 10 mA

0.3

AVDD3 = 3.3 V, IOL = 1 mA

0.1

AVDD3 = 1.8 V, IOL = 1 mA

0.1

OUTPUT TIMING SKEW

10 pF load

Between LVPECL Outputs

125

Rising edge only; any divide value

Between LVDS Outputs

138

Rising edge only; any divide value

Between CMOS (3.3 V) Outputs

Strong Drive Strength Setting

240

Weak Drive Strength Setting

Between CMOS (1.8 V) Outputs

Weak drive option not supported at 1.8 V

Between LVPECL Outputs and LVDS

Outputs

140

Between LVPECL Outputs and

CMOS Outputs

ZERO-DELAY TIMING SKEW

±5

Output relative to active input reference;

output distribution synchronization to

active reference feature enabled;

assumes manual phase offset

compensation of deterministic latency

1 The listed values are for the slower edge (rising or falling).

DAC OUTPUT CHARACTERISTICS (DACOUTP, DACOUTN)

Table 12.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

FREQUENCY RANGE

62.5

450

MHz

OUTPUT OFFSET VOLTAGE

This is the single-ended voltage at either

DAC output pin (no external load) when

the internal DAC code is such that no

current is delivered to that pin

VOLTAGE COMPLIANCE RANGE

VSS − 0.5

0.5

VSS + 0.5

OUTPUT RESISTANCE

Single-ended; each pin has an internal

50 Ω termination to VSS

OUTPUT CAPACITANCE

FULL-SCALE OUTPUT CURRENT

Programmable (8 mA to 31 mA; see the

DAC Output section)

GAIN ERROR

−12

+12

% FS

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