AD9547SLASHPCBZ datasheet(70/104 Pages) AD

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AD9547

Rev. 0 | Page 70 of 104

The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (Address 0x0D02 to Address 0x0D09).

When set to Logic 1, the IRQ mask bits enable the corresponding IRQ monitor bits to indicate an IRQ event. The default for all IRQ mask

bits is Logic 0, which prevents the IRQ monitor from detecting any internal interrupts.

Table 50. IRQ Mask for SYSCLK

Address

Bit

Bit Name

Description

0x0209

[7:6]

Unused

Unused.

SYSCLK unlocked

Enables IRQ for indicating a SYSCLK PLL state transition from locked to unlocked.

SYSCLK locked

Enables IRQ for indicating a SYSCLK PLL state transition from unlocked to locked.

[3:2]

Unused

Unused.

SYSCLK cal complete

Enables IRQ for indicating that SYSCLK calibration is complete.

SYSCLK cal started

Enables IRQ for indicating that SYSCLK calibration has begun.

Table 51. IRQ Mask for Distribution Sync, Watchdog Timer, and EEPROM

Address

Bit

Bit Name

Description

0x020A

[7:4]

Unused

Unused.

Distribution sync

Enables IRQ for indicating a distribution sync event.

Watchdog timer

Enables IRQ for indicating expiration of the watchdog timer.

EEPROM fault

Enables IRQ for indicating a fault during an EEPROM load or save operation.

EEPROM complete

Enables IRQ for indicating successful completion of an EEPROM load or save operation.

Table 52. IRQ Mask for the Digital PLL

Address

Bit

Bit Name

Description

0x020B

Switching

Enables IRQ for indicating that the DPLL is switching to a new reference.

Closed

Enables IRQ for indicating that the DPLL has entered closed-loop operation.

Free run

Enables IRQ for indicating that the DPLL has entered free-run mode.

Holdover

Enables IRQ for indicating that the DPLL has entered holdover mode.

Frequency unlocked

Enables IRQ for indicating that the DPLL lost frequency lock.

Frequency locked

Enables IRQ for indicating that the DPLL has acquired frequency lock.

Phase unlocked

Enables IRQ for indicating that the DPLL lost phase lock.

Phase locked

Enables IRQ for indicating that the DPLL has acquired phase lock.

Table 53. IRQ Mask for History Update, Frequency Limit, and Phase Slew Limit

Address

Bit

Bit Name

Description

0x020C

[7:5]

Unused

Unused.

History updated

Enables IRQ for indicating the occurrence of a tuning word history update.

Frequency unclamped

Enables IRQ for indicating a state transition of the frequency limiter from clamped to

unclamped.

Frequency clamped

Enables IRQ for indicating a state transition of the frequency limiter from unclamped to

clamped.

Phase slew unlimited

Enables IRQ for indicating a state transition of the phase slew limiter from slew limiting to

not slew limiting.

Phase slew limited

Enables IRQ for indicating a state transition of the phase slew limiter from not slew

limiting to slew limiting.

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