AD9547SLASHPCBZ datasheet(76/104 Pages) AD

76 / 104 page

AD9547

Rev. 0 | Page 76 of 104

Table 71. Q0 Divider1

Address

Bit

Bit Name

Description

0x0408

[7:0]

Q0 divider, Bits[7:0].

0x0409

[7:0]

Q0 divider, Bits[15:8].

0x040A

[7:0]

Q0 divider, Bits[23:16].

0x040B

[7:6]

Unused

Unused.

[5:0]

Q0 divider, Bits[29:24].

1 The default value is 0 (or divide by 1).

Table 72. Q1 Divider1

Address

Bit

Bit Name

Description

0x040C

[7:0]

Q1 divider, Bits[7:0].

0x040D

[7:0]

Q1 divider, Bits[15:8].

0x040E

[7:0]

Q1 divider, Bits[23:16].

0x040F

[7:6]

Unused

Unused.

[5:0]

Q1 divider, Bits[29:24].

1 The default value is 0 (or divide by 1).

Table 73. Reserved

Address

Bit

Bit Name

Description

0x0410 to

0x0417

[7:0]

Unused

Unused.

REFERENCE INPUT CONFIGURATION (REGISTER 0x0500 TO REGISTER 0x0507)

When all bits are set, the reference receiver section enters a deep sleep mode.

Table 74. Reference Power-Down

Address

Bit

Bit Name

Description

0x0500

[7:4]

Unused

Write a 1 to these bits.

Ref BB power-down

REF BB input receiver power-down.

0 (default) = normal operation.

1 = power-down.

Ref B power-down

REF B input receiver power-down.

0 (default) = normal operation.

1 = power-down.

Ref AA power-down

REF AA input receiver power-down.

0 (default) = normal operation.

1 = power-down.

Ref A power-down

REF A input receiver power-down.

0 (default) = normal operation.

1 = power-down.

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