AD9547SLASHPCBZ datasheet(13/104 Pages) AD

13 / 104 page

AD9547

Rev. 0 | Page 13 of 104

JITTER GENERATION

Table 19.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CONDITIONS: fREF = 8 kHz1, fDDS = 155.52 MHz2,

fLOOP = 100 Hz3

fSYSCLK = 50 MHz4 crystal; fS = 1 GHz5;

Q-divider = 1; default SYSCLK PLL charge

pump current; results valid for LVPECL,

LVDS, and CMOS output logic types

Bandwidth: 100 Hz to 77 MHz

0.71

ps rms

Random jitter

Bandwidth: 5 kHz to 20 MHz

0.34

ps rms

Random jitter

Bandwidth: 20 kHz to 80 MHz

0.43

ps rms

Random jitter

Bandwidth: 50 kHz to 80 MHz

0.43

ps rms

Random jitter

Bandwidth: 4 MHz to 80 MHz

0.31

ps rms

Random jitter

CONDITIONS: fREF = 19.44 MHz1, fDDS = 155.52 MHz2,

fLOOP = 1 kHz3

fSYSCLK = 50 MHz4 crystal; fS = 1 GHz5;

Q-divider = 1; default SYSCLK PLL charge

pump current; results valid for LVPECL,

LVDS, and CMOS output logic types

Bandwidth: 100 Hz to 77 MHz

1.05

ps rms

Random jitter

Bandwidth: 5 kHz to 20 MHz

0.34

ps rms

Random jitter

Bandwidth: 20 kHz to 80 MHz

0.43

ps rms

Random jitter

Bandwidth: 50 kHz to 80 MHz

0.43

ps rms

Random jitter

Bandwidth: 4 MHz to 80 MHz

0.32

ps rms

Random jitter

CONDITIONS: fREF = 19.44 MHz1, fDDS = 311.04 MHz2,

fLOOP = 1 kHz3

fSYSCLK = 50 MHz4 crystal; fS = 1 GHz5;

Q-divider = 1; default SYSCLK PLL charge

pump current; results valid for LVPECL,

LVDS, and CMOS output logic types

Bandwidth: 100 Hz to 100 MHz

0.67

ps rms

Random jitter

Bandwidth: 5 kHz to 20 MHz

0.31

ps rms

Random jitter

Bandwidth: 20 kHz to 80 MHz

0.33

ps rms

Random jitter

Bandwidth: 50 kHz to 80 MHz

0.33

ps rms

Random jitter

Bandwidth: 4 MHz to 80 MHz

0.16

ps rms

Random jitter

1 fREF is the frequency of the active reference.

2 fDDS is the output frequency of the DDS.

3 fLOOP is the DPLL digital loop filter bandwidth.

4 fSYSCLK is the frequency at the SYSCLKP and SYSCLKN pins.

5 fS is the sample rate of the output DAC.

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