CDPCLK4 datasheet(50/274 Pages) ALTERA

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3–16

Chapter 3: Memory Blocks in the Cyclone III Device Family

Design Considerations

Cyclone III Device Handbook

December 2011

Altera Corporation

Volume 1

Same-Port Read-During-Write Mode

This mode applies to a single-port RAM or the same port of a true dual-port RAM. In

the same port read-during-write mode, there are two output choices: New Data mode

(or flow-through) and Old Data mode. In New Data mode, new data is available on

the rising edge of the same clock cycle on which it was written. In Old Data mode, the

RAM outputs reflect the old data at that address before the write operation proceeds.

When using New Data mode together with byteena, you can control the output of the

RAM. When byteena is high, the data written into the memory passes to the output

(flow-through). When byteena is low, the masked-off data is not written into the

memory and the old data in the memory appears on the outputs. Therefore, the

output can be a combination of new and old data determined by byteena.

Figure 3–15 and Figure 3–16 show sample functional waveforms of same port

read-during-write behavior with both New Data and Old Data modes, respectively.

Mixed-Port Read-During-Write Mode

This mode applies to a RAM in simple or true dual-port mode, which has one port

reading and the other port writing to the same address location with the same clock.

Figure 3–15. Same Port Read-During Write: New Data Mode

Figure 3–16. Same Port Read-During-Write: Old Data Mode

clk_a

wren_a

address_a

data_a

rden_a

q_a (asynch)

clk_a

wren_a

address_a

data_a

rden_a

q_a (asynch)

a0(old data)

a1(old data)

CDPCLK4 Scheda tecnica(PDF) 50 Page - Altera Corporation