CDPCLK4 datasheet(77/274 Pages) ALTERA

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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

5–17

Hardware Features

July 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

PLL Control Signals

You can use the following three signals to observe and control the PLL operation and

resynchronization.

pfdena

Use the pfdena signal to maintain the last locked frequency so that your system has

time to store its current settings before shutting down. The pfdena signal controls the

PFD output with a programmable gate. If you disable the PFD, the VCO operates at

its last set value of control voltage and frequency with some long-term drift to a lower

frequency.

areset

The areset signal is the reset or resynchronization input for each PLL. The device

input pins or internal logic can drive these input signals. When driven high, the PLL

counters reset, clearing the PLL output and placing the PLL out of lock. The VCO is

then set back to its nominal setting. When driven low again, the PLL resynchronizes

to its input as it re-locks.

You must include the areset signal in your designs if one of the following conditions

is true:

■

PLL reconfiguration or clock switchover enabled in your design

■

Phase relationships between the PLL input clock and output clocks must be

maintained after a loss-of-lock condition

1 If the input clock to the PLL is toggling or unstable upon power up, assert the areset

signal after the input clock is stable and within specifications.

locked

The locked output indicates that the PLL has locked onto the reference clock and the

PLL clock outputs are operating at the desired phase and frequency set in the

Quartus II MegaWizard™ Plug-in Manager.

1 Altera recommends that you use the areset and locked signals in your designs to

control and observe the status of your PLL.

This implementation is illustrated in Figure 5–13.

Figure 5–13. Locked Signal Implementation

OFF

PLL

locked

areset

VCC

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