CDPCLK4 datasheet(100/274 Pages) ALTERA

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6–2

Chapter 6: I/O Features in the Cyclone III Device Family

I/O Element Features

Cyclone III Device Handbook

July 2012

Altera Corporation

Volume 1

Figure 6–1 shows the Cyclone III device family IOE structure.

I/O Element Features

The Cyclone III device family IOE offers a range of programmable features for an I/O

pin. These features increase the flexibility of I/O utilization and provide an

alternative to reduce the usage of external discrete components to on-chip, such as a

pull-up resistor and a diode.

Programmable Current Strength

The output buffer for each Cyclone III device family I/O pin has a programmable

current strength control for certain I/O standards.

The LVTTL, LVCMOS, SSTL-2 Class I and Class II, SSTL-18 Class I and Class II,

HSTL-18 Class I

and Class II, HSTL-15 Class I and Class II, and HSTL-12 Class I

and Class II I/O standards have several levels of current strength that you can

control.

Figure 6–1. Cyclone III Device Family IOE in a Bidirectional I/O Configuration

ENA

VCCIO

Optional

PCI Clamp

Programmable

Pull-Up

Resistor

Bus Hold

Input Pin to

Input Register

Delay

or Input Pin to

Logic Array

Delay

Output

Pin Delay

clkin

oe_in

data_in0

data_in1

sclr/

preset

Chip-Wide Reset

aclr/prn

oe_out

clkout

OE Register

Current Strength Control

Open-Drain Out

Column

or Row

Interconnect

io_clk[5..0]

Slew Rate Control

ACLR

/PRN

ACLR

/PRN

Output Register

ENA

ACLR

/PRN

Input Register

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