CDPCLK4 datasheet(61/274 Pages) ALTERA

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CIII51006-4.1

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Cyclone III Device Handbook

Volume 1

July 2012

ISO

9001:2008

Registered

5. Clock Networks and PLLs in the

Cyclone III Device Family

This chapter describes the hierarchical clock networks and phase-locked loops (PLLs)

with advanced features in the Cyclone® III device family (Cyclone III and

Cyclone III LS devices).

This chapter includes the following sections:

■

“Clock Networks” on page 5–1

■

“PLLs in the Cyclone III Device Family” on page 5–9

■

“Cyclone III Device Family PLL Hardware Overview” on page 5–10

■

“Clock Feedback Modes” on page 5–11

■

“Hardware Features” on page 5–15

■

“Programmable Bandwidth” on page 5–22

■

“Phase Shift Implementation” on page 5–22

■

“PLL Cascading” on page 5–24

■

“PLL Reconfiguration” on page 5–26

■

“Spread-Spectrum Clocking” on page 5–33

■

“PLL Specifications” on page 5–33

Clock Networks

The Cyclone III device family provides up to 16 dedicated clock pins (CLK[15..0])

that can drive the global clocks (GCLKs). The Cyclone III device family supports four

dedicated clock pins on each side of the device except EP3C5 and EP3C10 devices.

EP3C5 and EP3C10 devices only support four dedicated clock pins on the left and

right sides of the device.

f For more information about the number of GCLK networks in each device density,

refer to the Cyclone III Device Family Overview chapter.

GCLK Network

GCLKs drive throughout the entire device, feeding all device quadrants. All resources

in the device (I/O elements, logic array blocks (LABs), dedicated multiplier blocks,

and M9K memory blocks) can use GCLKs as clock sources. Use these clock network

resources for control signals, such as clock enables and clears fed by an external pin.

Internal logic can also drive GCLKs for internally generated GCLKs and

asynchronous clears, clock enables, or other control signals with high fan-out.

July 2012

CIII51006-4.1

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