CDPCLK4 datasheet(51/274 Pages) ALTERA

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Chapter 3: Memory Blocks in the Cyclone III Device Family

3–17

Design Considerations

December 2011

Altera Corporation

Cyclone III Device Handbook

Volume 1

In this mode, you also have two output choices: Old Data mode or Don't Care mode.

In Old Data mode, a read-during-write operation to different ports causes the RAM

outputs to reflect the old data at that address location. In Don't Care mode, the same

operation results in a “Don't Care” or unknown value on the RAM outputs.

f For more information about how to implement the desired behavior, refer to the

Internal Memory (RAM and ROM) User Guide.

Figure 3–17 shows a sample functional waveform of mixed port read-during-write

behavior for the Old Data mode. In Don't Care mode, the old data is replaced with

“Don't Care”.

1 For mixed-port read-during-write operation with dual clocks, the relationship

between the clocks determines the output behavior of the memory. If you use the

same clock for the two clocks, the output is the old data from the address location.

However, if you use different clocks, the output is unknown during the mixed-port

read-during-write operation. This unknown value may be the old or new data at the

address location, depending on whether the read happens before or after the write.

Conflict Resolution

When you are using M9K memory blocks in true dual-port mode, it is possible to

attempt two write operations to the same memory location (address). Because there is

no conflict resolution circuitry built into M9K memory blocks, this results in unknown

data being written to that location. Therefore, you must implement conflict-resolution

logic external to the M9K memory block.

Figure 3–17. Mixed Port Read-During-Write: Old Data Mode

a (old data)

b (old data)

clk_a&b

wren_a

address_a

q_b (asynch)

rden_b

address_b

data_a

CDPCLK4 Scheda tecnica(PDF) 51 Page - Altera Corporation