CDPCLK4 datasheet(66/274 Pages) ALTERA

66 / 274 page

5–6

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family

Clock Networks

Cyclone III Device Handbook

July 2012

Altera Corporation

Volume 1

GCLK Network Clock Source Generation

Figure 5–2 shows Cyclone III device family PLLs, clock inputs, and clock control

block location for different device densities.

Figure 5–2. PLL, CLK[], DPCLK[], and Clock Control Block Locations in the Cyclone III Device Family (1)

Notes to Figure 5–2:

(1) There are five clock control blocks on each side.

(2) Only one of the corner CDPCLK pins in each corner can feed the clock control block at a time. You can use the other CDPCLK pins as

general-purpose I/O pins.

(3) Remote clock pins can feed PLLs over dedicated clock paths. However, these paths are not fully compensated.

PLL

(2)

CDPCLK7

CDPCLK0

CDPCLK1

DPCLK1

DPCLK[11.10]

DPCLK[9..8]

CLK[11..8]

CDPCLK6

DPCLK0

CLK[3..0]

Clock Control

Block (1)

GCLK[19..0]

CDPCLK5

DPCLK7

CLK[7..4]

DPCLK6

CDPCLK4

CDPCLK2

DPCLK[3..2]

CLK[15..12]

DPCLK[5..4]

CDPCLK3

Clock Control

Block (1)

(3)

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