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Chapter 4: Embedded Multipliers in the Cyclone III Device Family

4–3

Architecture

December 2011

Altera Corporation

Cyclone III Device Handbook

Volume 1

In addition to the embedded multipliers in the Cyclone III device family, you can

implement soft multipliers by using the M9K memory blocks as look-up tables

(LUTs). The LUTs contain partial results from the multiplication of input data with

coefficients that implement variable depth and width high-performance soft

multipliers for low-cost, high-volume DSP applications. The availability of soft

multipliers increases the number of available multipliers in the device.

Table 4–2 lists the total number of multipliers available in the Cyclone III device

family using embedded multipliers and soft multipliers.

f For more information about M9K memory blocks of the Cyclone III device family,

refer to the Memory Blocks in the Cyclone III Device Family chapter.

f For more information about soft multipliers, refer to the Implementing Multipliers in

FPGA Devices application note.

Architecture

Each embedded multiplier consists of the following elements:

■

Multiplier stage

■

Input and output registers

■

Input and output interfaces

Table 4–2. Number of Multipliers in the Cyclone III Device Family

Device Family

Device

Embedded Multipliers

Soft Multipliers

(16

× 16) (1)

Total Multipliers (2)

Cyclone III

EP3C5

—

EP3C10

EP3C16

112

EP3C25

132

EP3C40

126

252

EP3C55

156

260

416

EP3C80

244

305

549

EP3C120

288

432

720

Cyclone III LS

EP3CLS70

200

333

533

EP3CLS100

276

483

759

EP3CLS150

320

666

986

EP3CLS200

396

891

1287

Notes to Table 4–2:

(1) Soft multipliers are implemented in sum of multiplication mode. M9K memory blocks are configured with 18-bit data widths to support 16-bit

coefficients. The sum of the coefficients requires 18-bits of resolution to account for overflow.

(2) The total number of multipliers may vary, depending on the multiplier mode you use.

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