CDPCLK4 datasheet(43/274 Pages) ALTERA

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Chapter 3: Memory Blocks in the Cyclone III Device Family

3–9

Memory Modes

December 2011

Altera Corporation

Cyclone III Device Handbook

Volume 1

Figure 3–8 shows timing waveforms for read and write operations in single-port

mode with unregistered outputs. Registering the outputs of the RAM simply delays

the q output by one clock cycle.

Simple Dual-Port Mode

Simple dual-port mode supports simultaneous read and write operations to different

locations. Figure 3–9 shows the simple dual-port memory configuration.

Cyclone III device family M9K memory blocks support mixed-width configurations,

allowing different read and write port widths.

Table 3–3 lists mixed-width configurations.

Figure 3–8. Cyclone III Device Family Single-Port Mode Timing Waveforms

clk_a

wren_a

address_a

data_a

rden_a

q_a (old data)

a0(old data)

a1(old data)

q_a (new data)

Figure 3–9. Cyclone III Device Family Simple Dual-Port Memory (1)

Note to Figure 3–9:

(1) Simple dual-port RAM supports input or output clock mode in addition to the read or write clock mode shown.

data[]

wraddress[]

wren

byteena[]

wr_addressstall

wrclock

wrclocken

aclr

rdaddress[]

rden

q[]

rd_addressstall

rdclock

rdclocken

Table 3–3. Cyclone III Device Family M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 1 of 2)

Read Port

Write Port

8192

× 1

4096

× 2

2048

× 4

1024

× 8

512

× 16

256

× 32

1024

× 9

512

× 18

256

× 36

8192 × 1

vvv

——

—

4096 × 2

vvv

——

—

2048 × 4

vvv

——

—

1024 × 8

vvv

——

—

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