CDPCLK4 datasheet(20/274 Pages) ALTERA

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Chapter 1: Cyclone III Device Family Overview

Cyclone III Device Family Architecture

Cyclone III Device Handbook

July 2012

Altera Corporation

Volume 1

Clock Networks and PLLs

Cyclone III device family includes 20 global clock networks. You can drive global

clock signals from dedicated clock pins, dual-purpose clock pins, user logic, and

PLLs. Cyclone III device family includes up to four PLLs with five outputs per PLL to

provide robust clock management and synthesis. You can use PLLs for device clock

management, external system clock management, and I/O interfaces.

You can dynamically reconfigure the Cyclone III device family PLLs to enable

auto-calibration of external memory interfaces while the device is in operation. This

feature enables the support of multiple input source frequencies and corresponding

multiplication, division, and phase shift requirements. PLLs in Cyclone III device

family may be cascaded to generate up to ten internal clocks and two external clocks

on output pins from a single external clock source.

f For more PLL specifications and information, refer to the Cyclone III Device Data Sheet,

Cyclone III LS Device Data Sheet, and Clock Networks and PLLs in the Cyclone III Device

Family chapters.

I/O Features

Cyclone III device family has eight I/O banks. All I/O banks support single-ended

and differential I/O standards listed in Table 1–6.

The Cyclone III device family I/O also supports programmable bus hold,

programmable pull-up resistors, programmable delay, programmable drive strength,

programmable slew-rate control to optimize signal integrity, and hot socketing.

Cyclone III device family supports calibrated on-chip series termination (RS OCT) or

driver impedance matching (Rs) for single-ended I/O standards, with one OCT

calibration block per side.

f For more information, refer to the I/O Features in the Cyclone III Device Family chapter.

High-Speed Differential Interfaces

Cyclone III device family supports high-speed differential interfaces such as BLVDS,

LVDS, mini-LVDS, RSDS, and PPDS. These high-speed I/O standards in Cyclone III

device family provide high data throughput using a relatively small number of I/O

pins and are ideal for low-cost applications. Dedicated differential output drivers on

the left and right I/O banks can send data rates at up to 875 Mbps for Cyclone III

devices and up to 740 Mbps for Cyclone III LS devices, without the need for external

resistors. This saves board space or simplifies PCB routing. Top and bottom I/O banks

support differential transmission (with the addition of an external resistor network)

data rates at up to 640 Mbps for both Cyclone III and Cyclone III LS devices.

Table 1–6. Cyclone III Device Family I/O Standards Support

Type

I/O Standard

Single-Ended I/O

LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X

Differential I/O

SSTL, HSTL, LVPECL, BLVDS, LVDS, mini-LVDS, RSDS, and PPDS

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