CDPCLK4 datasheet(118/274 Pages) ALTERA

118 / 274 page

6–20

Chapter 6: I/O Features in the Cyclone III Device Family

I/O Banks

Cyclone III Device Handbook

July 2012

Altera Corporation

Volume 1

f For more information about the Cyclone III device family I/O interface with 3.3-, 3.0-,

or 2.5-V LVTTL/LVCMOS systems, refer to AN 447: Interfacing Cyclone III and

Cyclone IV Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.

High-Speed Differential Interfaces

The Cyclone III device family can send and receive data through LVDS signals. For

the LVDS transmitter and receiver, the input and output pins of the Cyclone III device

family support serialization and deserialization through internal logic.

The BLVDS extends the benefits of LVDS to multipoint applications such as in

bidirectional backplanes. The loading effect and the need to terminate the bus at both

ends for multipoint applications require BLVDS to drive out a higher current than

LVDS

to produce a comparable voltage swing. All the I/O banks of the Cyclone III

device family support BLVDS for user I/O pins.

The reduced swing differential signaling (RSDS) and mini-LVDS standards are

derivatives of the LVDS standard. The RSDS and mini-LVDS I/O standards are

similar in electrical characteristics to LVDS, but have a smaller voltage swing and

therefore provide increased power benefits and reduced electromagnetic interference

(EMI).

The point-to-point differential signaling (PPDS) standard is the next generation of the

RSDS

standard introduced by National Semiconductor Corporation. The Cyclone III

device family meets the National Semiconductor Corporation PPDS Interface

Specification and supports the PPDS standard for outputs only. All the I/O banks of

the Cyclone III device family support the PPDS standard for output pins only.

You can use I/O pins and internal logic to implement the LVDS I/O receiver and

transmitter in the Cyclone III device family. Cyclone III and Cyclone III LS devices do

not contain dedicated serialization or deserialization circuitry. Therefore, shift

registers, internal PLLs, and IOEs are used to perform serial-to-parallel conversions

on incoming data and parallel-to-serial conversion on outgoing data.

The LVDS standard does not require an input reference voltage, but it does require a

100- termination resistor between the two signals at the input buffer. An external

resistor network is required on the transmitter side for top and bottom I/O banks.

f For more information about the Cyclone III device family high-speed differential

interface support, refer to the High-Speed Differential Interfaces in the Cyclone III Device

Family chapter.

External Memory Interfacing

The Cyclone III device family supports I/O standards required to interface with a

broad range of external memory interfaces, such as DDR SDRAM, DDR2 SDRAM,

and QDRII SRAM.

f For more information about the Cyclone III device family external memory interface

support, refer to the External Memory Interfaces in the Cyclone III Device Family chapter.

CDPCLK4 Scheda tecnica(PDF) 118 Page - Altera Corporation

CDPCLK4 Scheda tecnica(HTML) 118 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL