CDPCLK4 datasheet(125/274 Pages) ALTERA

125 / 274 page

Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family

7–3

High-Speed I/O Interface

December 2011

Altera Corporation

Cyclone III Device Handbook

Volume 1

Table 7–1 lists which I/O bank supports these I/O standards in the Cyclone III device

family.

You can use I/O pins and internal logic to implement a high-speed differential

interface in the Cyclone III device family. The Cyclone III device family does not

contain dedicated serialization or deserialization circuitry. Therefore, shift registers,

internal phase-locked loops (PLLs), and I/O cells are used to perform

serial-to-parallel conversions on incoming data and parallel-to-serial conversion on

outgoing data. The differential interface data serializers and deserializers (SERDES)

are automatically constructed in the core logic elements (LEs) with the Quartus® II

software ALTLVDS megafunction.

Table 7–1. Differential I/O Standards Supported in Cyclone III Device Family I/O Banks

Differential I/O Standards

I/O Bank Location

External Resistor

Network at

Transmitter

Transmitter (TX)

Receiver (RX)

LVDS

1,2,5,6

Not Required

Yes

All

Three Resistors

RSDS

1,2,5,6

Not Required

Yes

Not

Supported

3, 4, 7, 8

Three Resistors

All

Single Resistor

mini-LVDS

1,2,5,6

Not Required

Yes

Not

Supported

All

Three Resistors

PPDS

1,2,5,6

Not Required

Yes

Not

Supported

All

Three Resistors

BLVDS (1)

All

Single Resistor

Yes

LVPECL (2)

All

Not

Supported

Yes

Differential SSTL-2 (3)

All

Yes

Differential SSTL-18 (3)

All

Yes

Differential HSTL-18 (3)

All

Yes

Differential HSTL-15 (3)

All

Yes

Differential HSTL-12 (3)

All

Yes

Notes to Table 7–1:

(1) Transmitter and Receiver FMAX depend on system topology and performance requirement.

(2) The LVPECL I/O standard is only supported on dedicated clock input pins.

(3) The differential SSTL-2, SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards are only supported on clock input pins and PLL output clock

pins. PLL output clock pins do not support Class II interface type of differential SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards.

CDPCLK4 Scheda tecnica(PDF) 125 Page - Altera Corporation

CDPCLK4 Scheda tecnica(HTML) 125 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL