CDPCLK4 datasheet(140/274 Pages) ALTERA

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Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family

Software Overview

Cyclone III Device Handbook

December 2011

Altera Corporation

Volume 1

■

Longer traces have more inductance and capacitance. These traces must be as

short as possible to limit signal integrity issues.

■

Place termination resistors as close to receiver input pins as possible.

■

Use surface mount components.

■

Avoid 90° corners on board traces.

■

Use high-performance connectors.

■

Design backplane and card traces so that trace impedance matches the impedance

of the connector and termination.

■

Keep an equal number of vias for both signal traces.

■

Create equal trace lengths to avoid skew between signals. Unequal trace lengths

result in misplaced crossing points and decrease system margins as the

transmitter-channel-to-channel skew (TCCS) value increases.

■

Limit vias because they cause discontinuities.

■

Keep switching transistor-to-transistor logic (TTL) signals away from differential

signals to avoid possible noise coupling.

■

Do not route TTL clock signals to areas under or above the differential signals.

■

Analyze system-level signals.

f For more information about PCB layout guidelines, refer to the High-Speed Board

Layout Guidelines and Guidelines for Designing High-Speed FPGA PCBs application

notes.

Software Overview

Cyclone III device family high-speed I/O system interfaces are created in core logic

by a Quartus II software megafunction because they do not have a dedicated circuit

for the SERDES. The Cyclone III device family uses the I/O registers and LE registers

to improve the timing performance and support the SERDES. Altera Quartus II

software allows you to design your high-speed interfaces using the ALTLVDS

megafunction. This megafunction implements either a high-speed deserializer

receiver or a high-speed serializer transmitter. There is a list of parameters in the

ALTLVDS megafunction that you can set to customize your SERDES based on your

design requirements. The megafunction is optimized to use Cyclone III device family

resources to create high-speed I/O interfaces in the most effective manner.

1 When you are using the Cyclone III device family with the ALTLVDS megafunction,

the interface always sends the MSB of your parallel data first.

f For more information about designing your high-speed I/O systems interfaces using

the ALTLVDS megafunction, refer to the LVDS SERDES Transmitter/Receiver

(ALTLVDS_TX amd ALTLVDS_RX) Megafunction User Guide and the Quartus II

Handbook.

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